TUFTSim Tools
| The Tools page contains all the necessary programs to run a successful simulation on the TUFTSim simulator. There are two
downloads for each program: the program file and the archive file. The program file contains only the program itself, whereas the archive
file includes the source code and the README for the program. Note: the perl scripts (addClocktoDgp, flt2fls, generateFLT) are posted as .tar files. There is no archive for those files because the executable and the source code are one and the same. |
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| Program Name | Description | DOWNLOAD | |||
| File Type | Version | Size | Date Posted | ||
| addClocktoDgp.pl | This program adds a clock as a primary input into a waveform (.dwe) file. The clock input alternates between low and high values. | program | 1.0 | .80 kb | 1/5/05 |
| no archive | - - - - NA - - - - | ||||
| bench2ver | Program that converts a file from type "benchmark" into "verilog." | program | 1.0 | 1094 kb | 1/5/05 |
| archive | 1.0 | 13.3 kb | 1/5/05 | ||
| crest | This program extracts a symbol table from a (*.dee) file. | program | 1.0 | 6.5 kb | 1/5/05 |
| archive | 1.0 | 16.9 kb | 1/5/05 | ||
| decode | This program generates a list of all elements in a network (.dee) file. The output is saved in the file: (network_name).extr | program | 1.0 | 742 kb | 1/5/05 |
| archive | 1.0 | 16.4 kb | 1/5/05 | ||
| flt2fls.pl | This program converts a fault file from type 'flt' (industry standard) to type 'fls' *used in the TUFTSim simulator). Note: The symbol table (.smt), fault (.flt), and verilog (.v) files all must be present in the network directory for this program to run correctly. | program | 1.0 | 8.6 kb | 1/5/05 |
| no archive | - - - - NA - - - - | ||||
| func_TSdgp2dwe | This program takes a waveform in dgp format (which func_waveformgen deals with) and turns it into a .dwe format (which the MCS simulator inputs) | program | 1.0 | 1100 kb | 1/5/05 |
| archive | 1.0 | 57.9 kb | 1/5/05 | ||
| func_waveformgen | The initial function called to generate a random waveform to put into the simulator. | program | 1.0 | 1100 kb | 1/5/05 |
| archive | 1.0 | 59.9 kb | 1/5/05 | ||
| generateFLT.pl | This program generates an FLT fault file from scratch. Note: The circuit verilog file (.v) must be present in the network directory to properly run this program. | program | 1.0 | 11.2 kb | 1/5/05 |
| no archive | - - - - NA - - - - | ||||
| Parse | This program converts Verilog (*.v) files to DEE (*.dee) files. | program | 1.0 | 203 kb | 1/5/05 |
| archive | 1.0 | 1199 kb | 1/5/05 | ||
| Tufault | This program takes in a .dee file and outputs a file with the same name but adds the .fls extension. This file contains all possible faults at the inputs of non_wire elements (ie gates, behavioral, ...). | program | 1.0 | 50.3 kb | 1/5/05 |
| archive | 1.0 | 6.1 kb | 1/5/05 | ||