Tufts Simlab Overview
Image Enhancement and Signal Processing Research:
Our researchers are developing state of the art signal processing techniques for image enhancement using the "Agaian Algorithms," which were introduced by world renowned Dr. Sos Agaian of the University of Texas at San Antonio.
Our research team introduced the first quantitative measures of image quality called the EME, AME, AMEE and the Logarithmic AME. Prior to the introduction of these measures, image quality was oftentimes measured subjectively by the human eye.
Multi-Discipline Simulation Research:
In today's marketplace, there is a growing demand to validate and test designs that integrate a multitude of discrete, standard and commercial off the shelf (COTS) components. Often, the proprietary nature of COTS further complicates the validation process by prohibiting designers from implementing a robust test and validation strategy. In order to preserve a vendor's intellectual property, they often provide customers a high level model, with limited access to its internals. These high level models create a need for tools that are capable of testing and validating COTS components in conjunction with an engineer's mmore detailed design. Unfortunately, simulation tools currently available are incapable of simulating multilevel designs, which typically include models written at many levels of abstractions, such as gate, RTL and behavioral. Those tools that do attempt to solve these problems resort to merging many simulators together, each targeted at handling a specific level of abstraction. This approach incurs high communication overhead between simulators, as well as impaired observation and accuracy.
Our objective is to further develop simulation algorithms that will be the basis of a cohesive simulator platform. This platform is capable of accepting a diversity of components, digital and analog, at many levels of abstraction. By providing this capability, our simulator is able to test across hierarchical boundaries and over chip-system interfaces. Its flexiblity makes it applicable for modeling and simulating MEMs (micro-electro-mechanical) devices. This platform will also provide features for comparative analysis of designs, improved observation and behavioral model verification. By using our Multilevel Concurrent Simulator (MCS), we overcome the limitations imposed by merged simulator approaches. MCS achieves this by incorporating techniques that are not specific to any abstraction level, making it attractive for testing interface interconnects and mixed mode logic. Furthermore, with the addition of Multiple Domain Concurrent Simulation (MDCS) algorithms, MCS is capable of creating scenarios of experiments without approaching exhaustive testing. This allows MCS to determine any erratic or catastrophic behaviors that may arise from many experiments interacting with one another. This capability shows promise for exercising and verifying designs by identifying cause/effect relationships for fault tolerant systems. These algorithms were designed to overcome the memory bottleneck associated with many concurrent algorithms while maintaining accurate timing models. Incorporating multilevel modeling with the MDCS algorithms would create an efficient platform for performing design verification and experimentation.
Our approach uses a single simulator kernel, which does not incur the communication overhead associated with competing techniques. In addition, it is capable of creating dynamic scenarios of experiments without exhaustive enumeration. This is achieved by collapsing/compressing many experiments using a single CPU. The efficiency and functionality of the experimentation feature is not available in any other commercial or academic simulator today. Our simulator framework is capable of accepting VHDL/VHDL-AMS and VERILOG models written with any combination of gate and behavioral levels. It also possesses the functionality to accurately and efficiently test and validate designs. This includes interconnect boundaries and third party components within an integrated environment.
Our strategy is to incorporate Multiple Domain Concurrent Simulation algorithms in our multilevel simulator kernel to create a robust framework for verification and test. Working with our industry partners, Digital Equipment Co. (Intel and Compaq) and Draper Laboratories, our research tasks will include further refinement of MDCS algorithms to allow scenario experimentation with behavioral models along with a simulation interface for analog and digital logic designs. We will also investigate timing issues associated with behavioral models.
CAD Tool Repository:
The tools, tutorials and simulators developed for this work can be found by using the menu links at the top of this page.