the path of the binary is: /loc/v2v/bin/vhdl2v. Basic usage is:

"/loc/v2v/bin/vhdl2v {vhdl_file}"

when run with no options, vhdl2verilog simply takes in the vhdl file and converts to verilog.

Usage: vhdl2v input_file [[input_files] output_file] [options] [-Help] [-Usage] [-Version]

where option can be one or all of

[-File {file_name}] [-Replace] [-Silent] [-No_Comments] [-Debug] [-No_Default_defines] 
[-No_Package_translation {package_file_names}] [-Include_Package_files] [-Function_Map {files}] 
[-Support_Subprogram_Calls] [-Log {logfile_name}] [-SYNTHesis] [-87]

OPTIONS

-File {file_name} [-f {file_name}]:
        Read command line arguments from the specified file

-Replace [-r]:
        Replace the existing output_file with the new output_file ; default 
        is to backup the output_file to .old
        
-Silent [-s]:
        Suppress printing out of messages indicating translator actions

-No_Comments [-nc]:
        Supress extraction of comments from input HDL file

-Debug [-d]:
        Prints debug messages from the tool

-No_Default_defines [-nd]:
        Verilog define directives for TRUE and FALSE are present in all output files;
        use of this switch suppresses printing of default defines

-No_Package_translation {package_names} [-np {package_names}]:
        Packages with  or having  as prefix are not translated;
        this can be used to suppress translation of specific packages

-Include_Package_files [-ip]:
        Use of this switch will direct the translator to write the translation of packages
        into files '_package.verilog' and '_modules.verilog';
        default is to include them in the output file 

-Function_Map {files} [-fm {files}]:
        Read the function mapping files specified for translation

-Support_Subprogram_Calls [-ssc]:
               Translate the headers of function and procedure calls into an included file

-Log {logfile_name} [-l {logfile_name}]:
        Logs translator messages into file ; default log file is 'vhdl2v.log'

-SYNTHesis [-synth]:
        Produces synthesizable code; presently restricted to suppressing initial statements
        and using '==' Verilog operators instead of '===' operators

-87 [-87]:
        Disable support for VHDL-93; enable VHDL-87 support instead